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White Electronic Designs
WV3HG128M72AER-AD6
ADVANCED*
1GB - 128Mx72 DDR2 SDRAM RDIMM, VLP
FEATURES
VLP (very low profile) 240-pin, dual in-line memory module Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4300 and PC2-3200 Utilizes 800*, 667*, 533 and 400 Mb/s DDR2 SDRAM components VCC = VCCQ = 1.8V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3, 4, 5* and 6* Adjustable data-output drive strength On-die termination (ODT) Posted CAS# latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM Auto &self refresh (64ms: 8,192 cycle refresh) Gold edge contacts RoHS compliant Package option * 240 Pin DIMM VLP * PCB - 18.29mm (0.720") Max
DESCRIPTION
The WV3HG128M72AER is a 128Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of eighteen 128Mx4 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a VLP 240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option
OPERATING FREQUENCIES
PC2-3200 Clock Speed CL-tRCD-tRP
* Consult factory for availability
PC2-4300 266MHz 4-4-4
PC2-5300* 333MHz 5-5-5
PC2-6400* 400MHz 6-6-6
200MHz 3-3-3
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PIN CONFIGURATION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS VCCQ CKE0 VCC NC NC VCCQ A11 A7 VCC A5 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol A4 VCCQ A2 VCC VSS VSS VCC NC VCC A10/AP BA0 VCCQ WE# CAS# VCCQ NC NC VCCQ VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol VSS DQ4 DQ5 VSS DM0/DQS9 NC/DQS9# VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1/DQS10 NC/DQS10# VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2/DQS11 NC/DQS11# VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3/DQS12 NC/DQS12# VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8/DQS17 NC/DQS17# VSS CB6 CB7 VSS VCCQ NC VCC NC NC VCCQ A12 A9 VCC A8 A6 Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VCCQ A3 A1 VCC CK0 CK0# VCC A0 VCC BA1 VCCQ RAS# S0# VCCQ ODT0 A13 VCC VSS DQ36 DQ37 VSS DM4/DQS13 NC/DQS13# VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5/14 NC/DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DM6/DQS15 NC/DQS15# VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC/DQS16# VSS DQ62 DQ63 VSS VCCSPD SA0 SA1 2
WV3HG128M72AER-AD6
ADVANCED
PIN NAMES
Pin Name CK0,CK0# CKE0 CB0-CB7 RAS# CAS# WE# S0# A0-A13 BA0,BA1 ODT0 SCL SDA SA0-SA2 DQ0-DQ63 DM0-DM8 DQS0-DQS17 DQS0#-DQS17# VCC, VCCQ VSS VREF VCCSPD NC RESET# Function Clock Inputs Clock Enable Check Bits Row Address Strobe Column Address Strobe Write Enable Chip Select Address Inputs SDRAM Bank Address On-die termination control SPD Clock Input SPD Data Input/Output SPD address Data Input/Output Data Masks Data strobes Data strobes complement Core and I/O Power Ground Input/Output Reference SPD Power No connect Reset Input
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WV3HG128M72AER-AD6
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
VSS RS0# DQS0 DQS0# DQ0 DQ1 DQ2 DQ3 DQS1 DQS1# DQ8 DQ9 DQ10 DQ11 DQS2 DQS2# DQ16 DQ17 DQ18 DQ19 DQS3 DQS3# DQ24 DQ25 DQ26 DQ27 DQS4 DQS4# DQ32 DQ33 DQ34 DQ35 DQS5 DQS5# DQ40 DQ41 DQ42 DQ43 DQS6 DQS6# DQ48 DQ49 DQ50 DQ51 DQS7 DQS7# DQ56 DQ57 DQ58 DQ59 DQS8 DQS8# CB0 CB1 CB2 CB3 DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ60 DQ61 DQ62 DQ63 DM8/DQS17 NC/DQS17# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ52 DQ53 DQ54 DQ55 DM7/DQS16 NC/DQS16# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ44 DQ45 DQ46 DQ47 DM6/DQS15 NC/DQS15# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ36 DQ37 DQ38 DQ39 DM5/DQS14 NC/DQS14# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ28 DQ29 DQ30 DQ31 DM4/DQS13 NC/DQS13# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ20 DQ21 DQ22 DQ23 DM3/DQS12 NC/DQS12# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ12 DQ13 DQ14 DQ15 DM2/DQS11 NC/DQS11# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DQ4 DQ5 DQ6 DQ7 DM1/DQS10 NC/DQS10# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS# DM0/DQS9 NC/DQS9# DM I/O 0 I/O 1 I/O 2 I/O 3 CS# DQS DQS#
Serial PD SCL WP A0 A1 A2 SDA
SA0 SA1 SA2
VCCSPD VCC/VCCQ VREF VSS
Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs
S0# BA0 - BA1 A0 - A13 RAS# CAS# WE# CKE0 ODT0 RESET# PCK7 PCK7#
1:2 R E G I S T E R
RST#
CK0
RS0# : DDR2 SDRAMs RBA0 - RBA1 : DDR2 SDRAMs RA0 - RA13 : DDR2 SDRAMs RRAS# : DDR2 SDRAMs RCAS# : DDR2 SDRAMs RWE# : DDR2 SDRAMs RCKE0 : DDR2 SDRAMs RODT0 : DDR2 SDRAMs
CK0# RESET#
P L L
OE
PCK0-PCK6, PCK8, PCK9
CK : DDR2 SDRAMs CK# : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9# PCK7 CK : Register PCK7# CK# : Register
NOTE: All resistor values are 22 ohms unless otherwise specified.
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All voltages referenced to VSS Parameter Supply Voltage I/O Reference Voltage I/O Termination Voltage SPD Supply Voltage Symbol VCC VREF VTT VCCSPD Min 1.7 0.49 x VCC VREF-0.04 1.7 Typical 1.8 0.50 x VCC VREF -
WV3HG128M72AER-AD6
ADVANCED
DC OPERATING CONDITIONS
Max 1.9 0.51 x VCC VREF+0.04 3.6 Unit V V V V Notes 3 1 2
Notes: 1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VCCQ of all IC's are tied to VCC.
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Command/Address, RAS#, CAS#, WE#, CK, CK# DM IOZ IVREF PD Output leakage current; 0VIL
Input leakage current; Any input 0VCAPACITANCE
TA = 25C, f = 100MHz, VCC = VCCQ = 1.8V Parameter Input Capacitance: CK, CK# Input Capacitance: CKE, CS# Input Capacitance: Addr. RAS#, CAS#, WE# Input/Output Capacitance: DQ, DQS, DM, DQS# Note: Based on SAMSUNG components Symbol CCK CI1 CI2 CIO Max 11 12 12 10 Units pF pF pF pF
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WV3HG128M72AER-AD6
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter Operating Case Temperature (Commercial) Symbol TOPER Rating 0 to +85C Units C Notes 1, 2
NOTE: 1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2 2. At 0 - 85C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS Parameter Input High (Logic 1) Voltage Input High (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.300 Max VCC + 0.300 VREF - 0.125 Unit V V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS Parameter AC Input High (Logic 1) Voltage AC Input High (Logic 0) Voltage Symbol VIH(AC) VIL(AC) Min VREF + 0.250 Max VREF - 0.250 Unit V V
INPUT/OUTPUT CAPACITANCE
TA=25C, f=100MHz Parameter Input capacitance (0A~A13, BA0~BA1, RAS#, CAS#, WE#) Input capacitance (CKE0), (ODT0) Input capacitance (CS0#) Input capacitance (CK0, CK0#) Input capacitance (DQS0 ~ DQS17, DQS0# ~ DQS17#) Input capacitance (DQ0~DQ63), (CB0~CB7)
Notes: Based on ELPIDA components
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 (534, 403) COUT1 (534, 403)
Min 6.5 6.5 6.5 6 6.5 6.5
Max 7.5 7.5 7.5 7 8 8
Unit pF pF pF pF pF pF
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VCC = +1.8V 0.1V Symbol ICC0 Proposed Conditions
WV3HG128M72AER-AD6
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
534 2,420 403 2,250 Units mA
Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1
ICC1
2,640
2,400
mA
ICC2P
784
724
mA
ICC2Q
1,110
1,040
mA
ICC2N
1,090 1,190 600 1,840
1,130 1,190 570 1,730
mA mA mA mA
ICC3P
ICC3N
Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for detailed timing conditions
IDAD6W
3,820
2,900
mA
IDAD6R
3,590
3,000
mA
ICC5B
4,150
3,880
mA
ICC6
99
99
mA
ICC7
5,900
5,570
mA
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
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VCC = +1.8V 0.1V Symbol ICC0 Proposed Conditions
WV3HG128M72AER-AD6
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
534 2,390 403 2,120 Units mA
Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1
ICC1
2,660
2,390
mA
ICC2P
680
644
mA
ICC2Q
950
860
mA
ICC2N
1,040 1,220 950 1,670
950 1,130 860 1,580
mA mA mA mA
ICC3P
ICC3N
Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for detailed timing conditions
IDAD6W
3,560
3,020
mA
IDAD6R
3,560
3,020
mA
ICC5B
5,000
4,640
mA
ICC6
108
108
mA
ICC7
5,900
5,540
mA
Note: ICC specification is based on ELPIDA components. Other DRAM Manufacturers specification may be different.
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AC TIMING PARAMETERS
VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER Clock cycle time Clock CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS A DQ and DM input pulse width (for each input) Data hold skew factor DQ...DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising ... setup time DQS falling edge from CK rising ... hold time DQS...DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition CL = 4 CL = 3 SYMBOL tCK (4) tCK (3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS 0.9 0.4 0 0.35 0.4 WL - 0.25 MIN 3,750 5,000 0.45 0.45 MIN (tCH, tCL) -125 -500 tAC MIN 100 225 0.35 tHP - tQHS tQH - tDQSQ 0.35 0.35 -450 0.2 0.2
WV3HG128M72AER-AD6
ADVANCED
534 MAX 8,000 8,000 0.55 0.55 125 +500 tAC MAX tAC MAX MIN 5,000 5,000 0.45
403 MAX 8,000 8,000 0.55 0.55 125 +600 tAC MAX tAC MAX UNIT ps ps tCK tCK ps ps ps ps ps ps ps tCK ps ps ns tCK tCK ps tCK tCK ps tCK tCK ps tCK tCK tCK
0.45 MIN (tCH, tCL) -125 -600 tAC MIN 150 275 0.35 tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2
Data
400
450
+450
+500
Data Strobe
300 1.1 0.6 0.9 0.4 0 0.35 0.4 WL - 0.25
350 1.1 0.6
0.6 WL + 0.25
0.6 WL + 0.25
Continued on next page
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VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER Address and control input pulse width for each input Address and control input setup time Address and control input hold time CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay
Four Bank Activate period
WV3HG128M72AER-AD6
ADVANCED
AC TIMING PARAMETERS (cont'd)
534 SYMBOL tIPW tIS tIH tCCD tRC tRRD tRCD
tFAW
403 MAX MIN 0.6 350 475 2 55 7.5 15
37.5
Command and Address
MIN 0.6 250 375 2 60 7.5 15
37.5
MAX
37.5
37.5
ACTIVE to PRECHARGE command Internal READ to precharge command delay 6 Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period
PRECHARGE ALL command period
tRAS tRTP tWR tDAL tWTR tRP
tRPA
45 7.5 15 tWR + tRP 7.5 15
tRP+tCK
70,000
40 7.5 15 tWR + tRP 10 15
tRP+tCK
70,000
UNIT tCK ps ps tCK ns ns ns ns ns ns ns ns ns ns ns tCK ns ns ns s ns tCK ps ps tCK ps tCK ps ps
LOAD MODE command cycle time OCD Drive mode delay CKE low to CK,CK# uncertainty Refresh REFRESH to REFRESH command interval Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ command
Exit self refresh timing reference
tMRD tOIT tDELAY tRFC tREFI tXSNR tXSRD
tISXR
2 0 tIS + tCK + tIH 105
12 70,000 7.8
2 0 tIS + tCK + tIH 105
12 70,000 7.8
Self Refresh
tRFC (MIN) + 10 200
tIS
tRFC (MIN) + 10 200
tIS
Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off
tISXR tAOND tAON tAOFD tAOF tAONPD
250 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3
ODT turn-on (power-down mode)
ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any non-READ command. CKE minimum high/low time
tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE
2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
350 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3
2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
ODT
ps tCK tCK tCK tCK tCK tCK
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WV3HG128M72AER-AD6
ADVANCED
ORDERING INFORMATION FOR AD6
Part Number WV3HG128M72AER534AD6xxG WV3HG128M72AER403AD6xxG Speed/Data Rate 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 4 3 tRCD 4 3 tRP 4 3 Height* 18.29mm (0.72") 18.29mm (0.72")
NOTES: * RoHS products. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (E = Ellpida, M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR AD6
FRONT VIEW
133.50 (5.256) 133.20 (5.244)
3.00 (0.118)
(4X)
2.00 (0.079)
(4X)
Register
PLL
18.29 (0.720) TYP.
5.175 (0.204)
(2X)
PIN 1
1.0 (0.039) TYP. 0.80 (0.032) TYP. 1.50 (0.059) 10.00 (0.394) TYP.
123.0 (4.843) TYP.
PIN 120
BACK VIEW
Register
PIN 240
63.0 (2.480) TYP.
5.0 (0.197) TYP. 55.0 (2.165) TYP.
PIN 121
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
March 2005 Rev. 1
10
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WV3HG128M72AER-AD6
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 128M 72 A E R xxx AD6 x x G
WEDC MEMORY (SDRAM) DDR 2 GOLD DEPTH BUS WIDTH COMPONENT WIDTH x4 1.8V REGISTERED SPEED (Mb/s) PACKAGE 240 PIN (.72) INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (E = Elpida) (M = Micron) (S = Samsung) G = RoHS COMPLIANT
March 2005 Rev. 1
11
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
1GB - 128Mx72 DDR2 SDRAM REGISTERED, w/PLL DRAM DIE OPTIONS: * SAMSUNG: C-Die, will move to E-Die Q3'06 * MICRON: U27Y: B-Die, will move to U37Y: D-Die Q4"06 * ELPIDA: E-Die
WV3HG128M72AER-AD6
ADVANCED
Revision History Rev #
Rev 0 Rev 1
History
Created 1.0 Updated "Absolute Maximum Ratings" 1.1 Added Elpida "CAP" specifications 1.2 Added Elpida "ICC" specifications 1.3 Updated "AC Timing Parameters" 1.4 Added Elpida to part marking info & number guide 1.5 Added "Industrial Temperature" to part numbering guide 1.6 Added DRAM die rev option
Release Date
March 2005 April 2006
Status
Advanced Advanced
March 2005 Rev. 1
12
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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